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Parity Preserving Adder/Subtractor using a Novel Reversible Gate B.MOHAN1, J. LINGAIAH2, M.RAVI TEJA3 1

PG Scholar, Dept of (VLSI), Arjun College of Technology and Sciences, India, E-mail: [email protected] Associate Professor& HOD, Dept of ECE, Arjun College of Technology and Sciences, India, E-mail: [email protected] 3 Assistant Professor, Dept of ECE, Arjun College of Technology and Sciences, India, E-mail: [email protected]

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Abstract: Modern VLSI circuit design is governed by low power consumption requirements of ICs. Reversible logic has received great importance because of no information bit loss during computation which results in low power dissipation. Moreover, there is a need to convert the reversible circuits into fault tolerant reversible circuits to detect the occurrence of errors. Parity preserving property can be used for this. A new 5*5 parity preserving reversible gate is proposed in this paper, named as P2RG. The most significant aspect of this work is that it can work both as a full adder and a full subtractor by using one P2RG and Fredkin gate only. Proposed design is better in terms of gate count, garbage outputs, constant inputs and area than the existing similitude. Thus, this paper provides the initial threshold to design more complex systems which will be able to execute more complicated operations using parity preserving reversible logic. In today’s technical world, thermal considerations, reliability issues and efficiency have become major concerns. Nowadays, research is being done to design a system with high performance, speed and very low power dissipation or ideally no heat generation. As power consumption is a major constraint in designing of VLSI circuits so we need to switch to that computing world where no information loss exists because according to Landauer principle, on every bit of computation, conventional digital systems dissipate KTln2 amount of energy, where K is Boltzmann’s constant and T is the temperature at which the computation is performed. Bennett showed that this energy dissipation would not occur if the same number of information bits are generated, i.e. no information loss exists. Keywords: Reversible Logic, Parity Preserving, P2RG, Adder/Subtractor. I. INTRODUCTION Reversible circuits are composed of reversible gates. In these circuits there is no information loss. Reversible circuits can produce unique output from each input and vice versa, hence, there is a one-to-one correspondence between input and output vectors (Thapliyal and Srinivas, 2006). So a reversible logic gate has an equal number of inputs and outputs (k ×k) (Babu and Chowdhury, 2005). In ideal conditions, a reversible circuit has zero internal power dissipation because, it does not lose information. Under R. Landauer research in the early 1960s, the amount of energy dissipated for every irreversible bit operation is given by KTLn2 joules, where K = 1.3806505×10!23 J/K is the Boltzmann‟s constant and T is the absolute temperature at which operation is performed. But in 1973, Bennett showed that KTLn2 joules of energy can be saved from a system as long as the system permits the regeneration of the inputs from produced outputs (Haghparast et al., 2009; Haghparast and Navi, 2008a; Thapliyal and Gupta, 2006). A reversible gate with n-inputs and n-outputs is called a n × n reversible gate (Sastry et al., 2006). In a n × n reversible function, there are 2n input rows and 2n output rows in its truth table. In fact the output rows are a permutation of the input rows in the truth table (Kerntopf, 2002; Hung et al., 2006). Direct fanouts from the reversible gate and feedbacks from a gate output directly to its inputs are not allowed (Sastry et al.,

2006). Classical logic gates are called irreversible since they cannot uniquely reconstruct the input vector states from the output vector states. Synthesis and designing of a reversible gate is different from traditional logic gates (Haghparast and Sheikh, 2011). Therefore, constructing a fault tolerant reversible circuit is much more difficult than a conventional logic circuit (Parhami, 2006). In this paper, we propose a fault detection method based on parity preserving reversible logic gate. Present irreversible technologies dissipate a lot of heat in terms of bit loss which reduces life of the circuit. All logical operations in today's classical computers are irreversible. It means extraction of input from the respective output is not possible. On the other hand, reversible computation has a salient feature of unique one to one mapping between inputs and outputs which reduces the major problem of power dissipation with no information loss. A Reversible Logic is Characterized by Equal number of inputs and outputs. There exists one to one mapping between the respective inputs and outputs. Loops and fan out are not allowed. In classical computers, only NOT gate performs reversible operation since it has an equal number of inputs and outputs with their unique one to one mapping. Some reversible gates

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B.MOHAN, J. LINGAIAH, M.RAVI TEJA have already been proposed in literature like the controllednot (CNOT) (proposed by Feynman), Toffoli and Fredkin gates, IG Gate and MIG gate. Reversible gates have various applications in the designing of adders, subtractor, and multipliers etc, same like classical computers. The main focus of this paper is to design a circuit that can work as adder as well as subtractor simultaneously with minimum numbers of garbage outputs, constant inputs and area. II. DESIGN CONSTRAINTS AND DEFINITIONS A. Minimizing the Number of Ancillary (Constant) Inputs an extra, auxiliary bit or fixed qubit state that is added to the primary inputs in order to achieve the specific functionality but they need to be minimized for minimizing auxiliary storage. B. Minimizing the Number of Garbage Outputs: Outputs that are not used further, needed only to make the function reversible (which results to minimize area and power). C. Minimizing the Gate Count: Number of gates that are used to realize the system is gate count

Fig.1. (a) 5*5 Parity Preserving Reversible Gate (P2RG) (b) P2RG As Universal Gate TABLE I. Truth Table of P2RG Gate

D. Fault Tolerance: Any physical device while performing classical or quantum computation is subjected to error either due to noise in the environment or fault in the device. It can be detected by fault tolerant computing. Although reversibility is able to recover bit loss, but it is unable to detect bit errors in the circuit. Recent digital circuit designing is now focusing on the fault tolerant reversible circuits. E. Parity Preservation: It can be used for the fault tolerance computation. Faults in the circuit can be detected by comparing the parity of inputs and outputs. The idea of the parity preserving property in the design reversible logic circuits was given by Parhami. It is known that reversible gates have an equal number of inputs and outputs. A⊕B⊕C⊕D=P⊕Q⊕R⊕S (1) Where A, B, C and D are gate inputs and P, Q, R and S are gate outputs. III. PROPOSED DESIGN A new 5*5 parity preserving reversible gate, P2RG is introduced in Fig.1 (a). This gate is one through which means one of its inputs is also an output. It is shown in Fig.1 (b) that Proposed gate is universal since it is able to perform NOR operation. When input B= 1 and D= 0 then output Q performs NOR operation i.e. (A+C)‟. As it is known that NAND and NOR gates are universal gates so it can be concluded that it can be exploited to realize any arbitrary Boolean function. Truth table of this gate is shown in Table 1, where A, B, C, D and E are the inputs and P, Q, R, S and T are the outputs. It can be seen from the table that all the input and output vectors are uniquely related. The parity preserving property is promptly verified from the table by comparing the parity of the input to the parity of the output.

A. Parity Preserving Half Adder/Subtract or The parity preserving half adder/subtractor is realized using one P2RG gate and one Fredkin gate as shown in Fig.2. Half adder and subtractor are the basic building block to design full adder and subtractor. We need two inputs i.e. A and B to design a half adder/subtractor. No previous carry or borrow is needed in this. So, this design has two inputs A and B and a control line Ctrl which will control mode of operation, i.e. when Ctrl is at logic 0, the circuit will act as half adder and when ctrl is at logic 1, the circuit will act a s

International Journal of VLSI System Design and Communication Systems Volume.04, IssueNo.11, October-2016, Pages: 1183-1186

Parity Preserving Adder/Subtractor using a Novel Reversible Gate half subtractor. It will give three constant inputs and four C. Parity Preserving 16 -bit Parallel Adder/Subtractor garbage bits g1 to g4. Boolean expressions to realize the functionality of half adder and half subtractor are given below: Sum/Difference = A ⊕ B Carry = AB Borrow = A‟B

Fig.4. Parity Preserving 16 bit Parallel Adder/ Subtractor using P2RG Gate

Fig.2. Parity Preserving Half Adder/Subtractor using P2RG gate B. Parity Preserving Full Adder/Subtractor Many adder designs using reversible gates by several authors have been studied. The proposed design will work as adder as well as subtractor on a single unit. The parity preserving full adder/subtractor is realized using one P2RG gate and one Fredkin gate. In Fig.3, the circuit has three inputs A, B, Cin and a control line Ctrl which will control mode of operation. If Ctrl= 0, it will work as a full adder else it would function as a full subtractor. It has 2 constant inputs, C is set to 0 and E can be set to either 0 or 1. The basic Boolean expressions for sum/difference, carry and borrow are given below for full adder and subtractor: (Sum/Difference = (A ⊕ B ⊕ Cin)) (Carry = ((A ⊕ B).Cin) ⊕ AB)) (Borrow = ((A)‟.B) ⊕ (((A ⊕ B)‟).Cin))

An n-bit parallel adder/subtractor will need a chain of (n1) full adders/subtractor and one half adder/subtractor. Therefore 16-bit parity preserving parallel adder/subtractor is designed by using one parity preserving half adder/subtractor (P2RG HAS) and fifteen parity preserving full adder/subtractor (P2RG FAS). It has two 16-bit numbers which are A0 to A15 and B0 to B15 as inputs and a control line ctrl which will control the mode of operation. When ctrl line is set at logic 0, the circuit will perform 16-bit addition operation and when ctrl line is set at logic 1, the circuit will perform 16-bit subtraction. The Carry/Borrow received after addition/ subtraction is represented by C1/B1 to C15/B15.Output carry/borrow of each block, i.e. C1/B1 to C15/B15 will be the third input for the next block. The outputs, Sum/Difference and Carry/Borrow are shown in the Fig.4 as S0/D0 to S15/D15 respectively. Fig.4 shows the parity preserving 16-bit parallel adder/subtractor. IV. RESULTS In previous sections, an approach for designing parity preserving reversible full adder/subtractor has been discussed. Then an approach for parity preserving 8-bit parallel reversible full adder/subtractor has been discussed.

Proposed circuit is optimized in terms of number of constant inputs and garbage outputs. Fig.3 shows the implementation of parity preserving full adder/ subtractor in which g1, g2, g3 and g4 are garbage outputs.

Fig.5. Parity Preserving 8-Bit Adder/Subtractor using P2RG Gate

Fig.3. Parity Preserving Full Adder/Subtractor using P2RG gate

In this section, evaluation of the proposed circuits with the help of the comparative results is presented. Table II represents that the performance of proposed parity preserving reversible full adder circuit is better compared to existing counterparts. This design has been optimized in terms of constant inputs, garbage outputs and area. For area calculation, CMOS realization is done in Micro wind by using 90nm technology node Table III shows that performance of parity preserving 8-bit parallel adder/subtractor is better than existing designs.

International Journal of VLSI System Design and Communication Systems Volume.04, IssueNo.11, October-2016, Pages: 1183-1186

B.MOHAN, J. LINGAIAH, M.RAVI TEJA [11]G. Paul, A. Chattopadhyay, and C. Chandak, “Designing TABLE II. Comparative Experimental Results of Various parity preserving reversible circuits,” arXiv preprint arXiv: Parity Preserving Full Adder/Subtractor 1308.0840, 2013. [12]B. Parhami, “Fault-tolerant reversible circuits,” in Signals, Systems and Computers, 2006. ACSSC’06. Fortieth Asilomar Conference on. IEEE, 2006, pp. 1726–1729. TABLE III. Comparative Experimental Results of Various Parity Preserving 8-Bit Full Adder/Subtractor

V. CONCLUSION In this study, we proposed a novel Parity Preserving Reversible gate. We also designed Parity Preserving HalfAdder/Subtractor circuit and a Parity Preserving reversible full-Adder/Subtractor circuit using P2RG gate. The proposed design can work as single unit that can acts as adder as well as subtractor depending upon our requirement. The proposed design offers less hardware complexity, less gate count, less garbage bits and constant inputs. In this paper we have worked on the Reversible logic gates on combinational circuits in future we can extend these to implement sequential circuits also. VI. REFERENCES [1]Ragani Khandelwal, Sandeep Saini, “Parity Preserving Adder/Subtractor using a Novel Reversible Gate”, 2015 Fifth International Conference on Communication Systems and Network Technologies. [2]R. Landauer, “Irreversibility and heat generation in the computing process,” IBM journal of research and development, vol. 5, no. 3, pp. 183–191, 1961. [3]C. H. Bennett, “Logical reversibility of computation,” IBM journal of Research and Development, vol. 17, no. 6, pp. 525–532, 1973. [4]R. P. Feynman, “Quantum mechanical computers,” Foundations of physics, vol. 16, no. 6, pp. 507–531, 1986. [5]E. Fredkin and T. Toffoli, Conservative logic. Springer, 2002. [6]M. Islam, Z. Begum et al., “Reversible logic synthesis of fault tolerant carry skip BCD adder,” arXiv preprint arXiv: 1008.3288, 2010. [7]P. NG and M. Anandaraju, “Design and synthesis of fault tolerant full adder/subtractor using reversible logic gates.” [8]P. Garg and S. Saini, “A novel design of compact reversible sg gate and its applications,” in Communications and Information Technologies (ISCIT), 2014 14th International Symposium on. IEEE, 2014, pp. 400–403. [9]S. Saini and S. B. Mandalika, “A new bus coding technique to minimize crosstalk in VLSI bus,” in Electronics Computer Technology (ICECT), 2011 3rd International Conference on, vol. 1. IEEE, 2011, pp. 424–428. [10]USYD, “State Reduction,” http://www.ee.usyd.edu.au/ tutorials/digital tutorial/part3/st-red.htm, 2008, [Online; accessed 19-July-2008].

Author’s Profile B. Mohan, PG Scholar, Dept of ECE(VLSI), from Arjun College of Technology and Sciences, Hyderabad, India, E-mail: [email protected]

Mr. J. Lingaiah, received the Master of Engineering (M.E) in Communication Engineering From The Chaitanya Bharithi Institute Of Technology-Osmania University, He Received The Bachelor Of Engineering Degree From Jyothismathi Institute Of Technology And Science-Jntu-H. He is currently working as Associate Professor and a Head of the Department of ECE with Arjun College of Technology And Sciences, hyd. His interest subjects are VLSI, Signal Processing, Analog and Digital Communication, Digital Electronics and etc, Email: [email protected] Mr. M.Ravi Teja, received the Master Of Technology degree in Embedded Systems from the ANURAG Engineering CollegeJNTUH , he received the Bachelor of Engineering degree from Madhira Institute of Technology & Sciences-JNTUH. He is currently working as assistant Professor of ECE with Arjun College of Technology & Sciences. His interest subjects are Embedded Systems,VLSI, Communication Systems, Digital Electronics and etc, E-mail: [email protected]

International Journal of VLSI System Design and Communication Systems Volume.04, IssueNo.11, October-2016, Pages: 1183-1186

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