J. Comp. & Math. Sci. Vol. 1(1), 21-26 (2009).
IMPLEMENTATION OF N-BIT ADDER AND SUBTRACTOR OF LIBRARY COMPONENTS FOR ARITHMETIC UNIT Vishal Kumar Srivastava*, Subhash Kumar Sharma**, S. N. Shukla*** and Himanshu Pandey**** *Department of Physics & Electronics Dr. R.M.L. Avadh University, Faizabad (India) **Department Of Electronics D.D.U. Gorakhpur University, Gorakhpur (India) ***Department of Physics & Electronics Dr. RML Avadh University, Faizabad (India) ****Department of Mathematics & Statistics D.D.U. Gorakhpur University, Gorakhpur (India) ABSTRACT This paper deals with development of an n-bit ALU using VHDL. Normally the most of the industries, now a days are using either 4-bit ALU or 8-bit ALU, so We have generalized this, thus We need not to worry about the bit size of ALU. It has solved all the problems of 4-bit, 8bit and 16-bit ALU's and so on. Hence, We have utilized VHSIC Hardware Description Language and Xilinx in accomplishing this task of development of an n-bit ALU. An Arithmetic and Logic Unit (ALU) is a combinational circuit that performs logic and arithmetic micro-operations on a pair of n-bit operands. The operations performed by an ALU are controlled by a set of function-select inputs. The ALU is the part of computer that actually performs arithmetic and logical operations on data. All of the other elements of the computer system-control unit registers, memory, I/Os are mainly to bring data into the ALU for it to process and then to take the results back out. Key words: Half adder, Full adder, Ripple adder, n-bit adder, Subtractor, n-bit Subtactor.
INTRODUCTION Addition is the most commonly performed arithmetic operation in digital systems. An adder
combines two arithmetic operands using the addition rules. An adder can perform subtraction as the addition of the minuend and the complemented (negated) subtrahend, but we can also
[ 22 ] build subtractor circuits that perform subtraction directly. MSI devices called ALUs perform addition, subtraction, or any of several other operations according to an operation code supplied to the device.
the full-adder equations is shown in Fig. (1). The corresponding logic symbol is shown in Fig. (2).
Half Adder and Full Adder: The simplest adder, called a half adder, adds two 1-bit operands X and Y, producing a 2-bit sum. The sum can range from 0 to 2, which requires two bits to express. The low-order bit of the sum may be named HS (half sum), and the high-order bit may be named CO (carry out). We can write the following equations for HS and CO:
Fig. (1) Full adder: gate level circuit diagram
HS = X XOR Y = X Y'+X'Y
Fig. (2) Full adder: logic symbol
CO = X Y To add operands with more than one bit, we must provide for carries between bit positions. The building block for this operation is called a full adder. Besides the addend-bit inputs X and Y, a full adder has a carry-bit input, CIN. The sum of the three inputs can range from 0 to 3, which can still be expressed with just two output bits, S and COUT, having the following equations: S
= X XOR Y XOR CIN = X Y' CIN'+X' Y CIN'+X' Y' CIN+X Y CIN
COUT= X Y + X CIN + Y CIN Here, S is 1 if an odd number of the inputs are 1, and COUT is 1 if two or more of the inputs are 1. One possible circuit that performs
Ripple Adder: Two binary words, each with n bits, can be added using a ripple adder-a cascade of n full-adder stages, each of which handles one bit. Fig.(3) shows the circuit for a 4-bit ripple adder. The carry input to the least significant bit (c0) is normally set to 0, and the carry output of each full adder is connected to the carry input of the next most significant full adder. A ripple adder is slow, since in the worst case a carry must propagate from the least significant full adder to the most significant one. This occurs if, for example, one addend is 11...11 and the other is 00 …01. Assuming that all of the addend bits are presented simultaneously, the total worstcase delay is
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Fig. (3) 4 bit ripple adder
where tXYCout is the delay from X or Y to COUT in the least significant stage, tCinCout is the delay from CIN to COUT in the middle stages, and tCinS is the delay from CIN to S in the most significant stage. A faster adder can be built by obtaining each sum output si with just two levels of logic. This can be accomplished by writing an equation for si in terms of x0-xi, y0-yi, and c0, "multiplying out" or "adding out" to obtain a sumof-products or product-of-sums expression, and building the corresponding AND-OR or OR-AND circuit. Unfortunately, beyond s2, the resulting expressions have too many terms, requiring too many first-level gates and more inputs than typically possible on the second-level gate.
(borrow out). We can write logic equations corresponding to the binary subtraction table as follows: D = X XOR Y BIN BOUT = X' Y + X' BIN + Y BIN These equations are very similar to equations for a full adder. A two's-complement subtraction operation, X - Y, can be performed by an addition operation, namely, by adding the two's complement of Y to X. The two's complement of Y is Y + 1, where Y is the bit-by-bit complement of Y. A binary adder can be used to perform an unsigned subtraction operation X - Y, by performing the operation X + Y + 1. We can build a full subtractor from a full adder.
Subtractor: A full subtractor handles one bit of the binary subtraction algorithm, having input bits X (minuend), Y (subtrahend), and BIN (borrow in), and output bits D (difference) and BOUT
Any n-bit adder circuit can be made to function as a subtractor by complementing the subtrahend and treating the carry-in and carryout signals as borrows with the opposite active level.
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Fig. (4) Subtractors using adders; (a) full adder (b) full subtractor (c) interpreting 74x999 as a full subtractor (d) ripple adder. Simulation Results of ALU Components Using Xilinx n-bit Full Adder: Input1 a1=10101, b1=11001 Required Sum=01110, Required Carry=1 Obtained Sum=01110, Obtained Carry=1
Input2 a1=11100, b1=10001 Required Sum=01101, Required Carry=1 Obtained Sum=01101, Obtained Carry=1
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n-bit Full Subtractor: Input1 a1=11100, b1=10010 Required Difference = 01010, Required Borrow = 0 Obtained Difference = 01010, Obtained Difference = 0
Input2 a1=10010, b1=11100 Required Difference=10110, Required Borrow=1 Obtained Difference=10110 (2's complement), Obtained Borrow=1
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CONCLUSIONS This paper deals with development of an n-bit adder and subtractor for ALU in VHDL with the help of ModelSim and synthesized with Xilinx tools. We have designed adder, subtractor VHDL programs. All programs are on an n-bit format; hence they can be treated as Universal programs. Normally most of the industries now-a-days are using either 4-bit ALU or 32-bit ALU, we have generalized it. Hence now we need not to worry about the bit size of ALU. This will solve all the problems of 4-bit, 8-bit and 16-bit ALU's and so on. Simulation results of all the designed programs have been carried out for various inputs with the help of ModelSim tool. In future, we can design ALU which can handle floating point numbers and shifters. Shifters include Right Level Logic and Left Level Logic. Also, various mathematical expressions handling ALU can be designed. E.g. modulus, percentage etc. ALU which can follow BODMAS rule can also be designed. Hence, in future we can add any type of mathematical and logical modules provided they must be on an n-bit format. Tools Used : Platform: Windows XP Simulator: Model Sim SE, Version 5.5f and
5.5a, Mentor Graphics Company Synthesizer: Leonardo Spectrum 2003a.33, Mentor Graphics, Inc., Xilinx 6.3i REFERENCES 1. The VHDL Cookbook, First Edition, Peter J. Ashenden, Dept. Computer science, University of Adelaid, South Australia (1990). 2. D. Gajski and R. Khun, "Introduction: New VLSI Tools," IEEE Computer, Vol. 16, No. 12, pp. 11-14, Dec. (1983). 3. M. Mano and C. Kime, "Logic and Computer Design Fundamentals," 2nd Edition, Prentice Hall, Upper Saddle River (2001). 4. S. Yalamanchili, "VHDL Starter's Guide," Prentice Hall, Upper Saddle River (1998). 5. J. Bhasker, "VHDL Primer," 3rd Edition, Prentice Hall, Upper Saddle River (1998). 6. P. J. Ashenden, "The Student's Guide to VHDL," Morgan Kaufmann Publishers, Inc, San Francisco (1998). 7. A. Dewey, "Analysis and Design of Digital Systems," PWS Publishing Company, New York (1997). 8. C. H. Roth, "Digital System Design using VHDL", PWS Publishing Company, New York (1998). 9. D. Pellerin and D. Taylor, "VHDL Made Easy!", Prentice Hall, Upper Saddle River, (1997).