# HDL Based Digital Design with Programmable Logic Lecture 10

EE 459/500 – HDL Based Digital Design with Programmable Logic Lecture 10 Arithmetic Units

Read before class: First part of Chapter 4 from textbook

Overview  Adders/Subtractors  Multipliers  Xilinx Unisim

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Adders/Subtractors - Integers  Basic building block for Computer-Arithmetic and Digital Signal Processing  Operate on binary vectors; use the same subfunction in each bit position

• Propagate and generate logic

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Functional Block Implementation  Half adder: X S=X + Y Y C=X∙Y  Full adder: S=X + Y + Cin C=XY + (X + Y)Cin =G+P∙Cin

• XY: carry generate G • X + Y: carry propagate P

X

Y

G

S C

P Cin C

X Y

S Cin

C

 Worst case delay: #bits x (full adder delay)

• •

The longest path is from A0/B0 through the circuit to S3 Or from C0 through the circuit to C4,

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Carry Lookahead Adder  From the full-adder implementation, two signal conditions: generate G and propagate P. Pi = A i + Bi Si = Pi + Ci G i = A iB i Ci+1 = Gi + PiCi  In order to reduce the length of the carry chain, Ci is changed to a more global function spanning multiple cells C1=G0+P0C0 C2=G1+P1C1=G1+P1(G0+P0C0) =G1+P1G0+P1P0C0 =G0-2 + P0-2C0 C3=G2+P2C2=G2+P2(G1+P1G0+P1P0C0) =G2+P2G1+P2P1G0+P2P1P0C0 = G0-3+P0-3C0 C4=G3+P3C3=G3+P3(G2+P2G1+P2P1G0+P2P1P0C0) =G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0C0 = G0-4 +P0-4C0

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VHDL Description of a 4-bit CLA entity CLA4 is port (A, B: in bit_vector (3 downto 0); Ci: in bit; S: out bt_vector (3 downto 0); Co, PG, GG: out bit); end CLA4; architecture structure of CLA4 is component GPFullAdder port (X, Y, Cin: in bit; G, P, Sum: out bit); end component; component CLALogic is port (G, P: in bit_vector (3 downto 0); Ci: int bit; C: out bit_vector (3 downto 1); Co, FG, CG: out bit); end component; signal G, P: bit_vector (3 downto 0); signal C: bit_vector (3 downto 0); begin CarryLogic: CLALogic port map (G, P, Ci, C, Co, PG, GG); FA0: GPFullAdder port map (A(0), B(0), Ci, G(0), P(0), S(0)); FA1: GPFullAdder port map (A(1), B(1), C(1), G(1), P(1), S(1)); FA2: GPFullAdder port map (A(2), B(2), C(2), G(2), P(2), S(2)); FA1: GPFullAdder port map (A(3), B(3), C(3), G(3), P(3), S(3)); end structure;

CLALogic entity CLALogic is port (G, P: in bit_vector (3 downto 0); Ci: in bit; C: out bit_vector (3 downto 1); Co, PG, GG: out bit); end CLALogic; architecture Equations of CLALogic is signal GG_int, PG_int: bit begin C(1)<=G(0) or (P(0) and Ci); C(2)<=G(1) or (P(1) and G(0) or (P(1) and P(0) and Ci); C(3)<=G(2) or (P(2) and P(1) and G(0) or (P(2) and P(1) and P(0) and Ci); PG_int<=P(3) and P(2) and P(1) and P(0); GG_int<=G(3) or (P(3) and G(2)) or (P(3) and P(2) and G(1)) or (P(3) and P(2) and P(1) and P(0) and G(0)); Co<=GG_int or (PG_int and Ci); PG<=PG_int; GG<=GG_int; end Equations;

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16-bit Carry Lookahead Adder  Extend to 16 bits, to have four 4-bit adders use one of the same carry lookahead circuits  Delay Specifications

NOT=1, XOR=3 AND=3, AND-OR=2

 Longest delays:

• •

Ripple carry adder =3+15*2+3=36 CLA =3+3*2+3=12

Subtraction  Subtraction (A-B)

Unsigned:  A≥B => A-B  A the difference A-B+2n is subtracted from 2n, a “–” sign added before the result (2n-X is taking the 2’s complement of X)

 Signed integer

• •

For binary numbers s an-2 … a2a1a0 s=0 for positive numbers; s=1 for negative numbers Signed-magnitude: the n-1 digits are a positive magnitude Signed 2’s complement

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2’s Complement Adder/Subtractor  Subtraction can be done by adding 2’s complement

 For S=1, subtract, the 2’s complement of B is formed by using XORs to form the 1’s complement and adding the 1 applied to C0  For S=0, add, B is passed through unchanged

VHDL code for adder/subtractor LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY addsubtract IS PORT ( S : IN STD_LOGIC; A, B : IN STD_LOGIC_VECTOR (3 DOWNTO 0); Sout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); Cout : OUT STD_LOGIC); END adderlpm; ARCHITECTURE structural OF addsubtract IS COMPONENT full_add PORT( a, b, c_in : IN STD_LOGIC; c_out : OUT STD_LOGIC); END COMPONENT; -- Define a signal for internal carry bits SIGNAL C : STD_LOGIC_VECTOR (4 downto 0); SIGNAL B_comp : STD_LOGIC_VECTOR (4 downto 1);

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VHDL code for adder/subtractor -- add/subtract select to carry input (S = 1 for subtract) C(0) <= S; adders: FOR i IN 1 to 4 GENERATE --invert B for subtract function (B(i) xor 1,) --do not invert B for add function (B(i) xor 0) B_comp(i) <= B(i) xor S; adder: full_add PORT MAP (A(i),B_comp(i),C(I -1),C(i),Sout(i)); END GENERATE; Cout <= C(4); END structural;

VHDL code for adder/subtractor LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY addsubtract IS PORT ( S : IN STD_LOGIC; A, B : IN STD_LOGIC_VECTOR (3 DOWNTO 0); Sout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); Cout : OUT STD_LOGIC); END adderlpm; ARCHITECTURE behavioral OF addsubtract IS signal Sum : STD_LOGIC_VECTOR (4 downto 0); BEGIN with S select Sum <= A + B when ‘0’ A – B + “10000” when others; Cout <= Sum(4); Sout <= Sum(3 downto 0); END behavioral;

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Overview  Adders/Subtractors  Multipliers  Xilinx Unisim

Multiplication  Multiply requires shifting the multiplicand to the left adding it to the partial sum  Requires a shift register as wide as the product and an accumulator for the partial and final product.

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Add-and-Shift Multiplier  Place the multiplier in the rightmost 4 bits of the 8-bit product register Example: 10 x 14

 Shift 1 -- The bit shifted out of the product register is 0. No add is performed.

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 Shift 2 -- The bit shifted out of the product register is 1. Add the multiplicand to the first 4 bits of the product register.

 Shift 3 -- Again add the multiplicand to the leftmost 4 bits of the product register.

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 Shift 4 -- Shift then add.

 Finally, shift right and end. The product is found in the 8-bit product register (140)

10 x 14 = 140

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State Graph

VHDL code for 4-bit binary multiplier

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Array Multiplier

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Array Multiplier

VHDL code for 4-bit array multiplier

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VHDL code for 4-bit array multiplier

Overview  Adders/Subtractors  Multipliers  Xilinx Unisim

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Xilinx simulation libraries  Xilinx provides the following simulation libraries for simulating primitives and cores (http://www.xilinx.com/support/documentation/s w_manuals/xilinx11/ise_c_simulation_libraries. htm):

• • • • • •

UNISIM library for functional simulation of Xilinx primitives UniMacro library for functional simulation of Xilinx macros XilinxCoreLib library for functional simulation of Xilinx cores Xilinx EDK library for behavioral simulation of Xilinx Embedded Development Kit (EDK) IP components SIMPRIM library for timing simulation of Xilinx primitives SmartModel/SecureIP simulation library for both functional and timing simulation of Xilinx Hard-IP, such as PPC, PCIe, GT, and TEMAC IP.

Xilinx Unisim Library of Primitives  Xilinx ISE XST system includes a library of primitives and macros called Unisim  Many modules in the library are technology dependent  Most modules are parameterized  More modules are available through CoreGenerator (see also Lab #5 of this course)  Spartan-6 Libraries Guide for HDL Designs: http://www.xilinx.com/support/documentation /sw_manuals/xilinx11/spartan6_hdl.pdf

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Example: VHDL Instantiation Template

Always check documentation for your FPGA family to see what’s available!

Example: Spartan-3E FPGA 

Use primitive named "RAMB16_S2" (an 8k x 2 SinglePort RAM for Spartan-3E FPGA) to create an 8k x 4 single port RAM

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; library unisim; use unisim.vcomponents.all; entity ram_test is end ram_test;

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architecture Behavioral of ram_test is --signal declarations. signal clk, en, ssr, we : std_logic:='0'; signal Dout, Din : std_logic_vector(3 downto 0):="0000"; signal addr : std_logic_vector(12 downto 0):=(others => '0'); begin --RAMB16_S2 is 8k x 2 Single-for Spartan-3E. --We use this to create 8k x 4 Single-Port RAMPort RAM. --Initialize RAM which carries LSB 2 bits of the data. RAM1 : RAMB16_S2 port map ( DO => Dout(1 downto 0), -- 2-bit Data Output ADDR => ADDR, -- 13-bit Address Input CLK => CLK, -- Clock DI => Din(1 downto 0), -- 2-bit Data Input EN => EN, -- RAM Enable Input SSR => SSR, -- Synchronous Set/Reset Input WE => WE -- Write Enable Input ) --Initialize RAM which carries MSB 2 bits of the data. RAM2 : RAMB16_S2 port map ( DO => Dout(3 downto 2), -- 2-bit Data Output ADDR => ADDR, -- 13-bit Address Input CLK => CLK, DI => Din(3 downto 2), EN => EN, SSR => SSR, WE => WE );

--100 MHz clock generation for testing process. clk_process : process begin wait for 5 ns; clk <= not clk; end process; --Write and Read. --RAM has a depth of 13 bits and has a width of 4 bits. simulate : process begin en <='1'; we <= '1'; --Write the value "i" at the address "i" for 10 clock cycles. for i in 0 to 10 loop addr <= conv_std_logic_vector(i,13); din <= conv_std_logic_vector(i,4); wait for 10 ns; end loop; we<= '0'; --Read the RAM for addresses from 0 to 20. for i in 0 to 20 loop addr <= conv_std_logic_vector(i,13); wait for 10 ns; end loop; end process; end Behavioral;

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Summary  Adders/subtractors are very important arithmetic units utilized in a variety of applications (processors, DSPs, etc.)  More ways to design them; tradeoffs between area and performance  Always check documentation for your FPGA family

Appendix A: Other Arithmetic Functions  Overflow detection: overflow occurs if n+1 bits are required to contain the results from an n-bit addition or subtraction  Incrementing: counting up, A+1, B+4  Decrementing: counting down, A-1, B-4  Multiplication by constant: left shift  Division by constant: right shift  Zero fill: filling zero either at MSB or LSB end  Extension: copy the MSB of the operand into the new positions

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## HDL Based Digital Design with Programmable Logic Lecture 10

EE 459/500 – HDL Based Digital Design with Programmable Logic Lecture 10 Arithmetic Units Read before class: First part of Chapter 4 from textbook O...

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