Loading...

Design of Reversible Adder Subtractor Using Multifunction Reversible Logic Gate (MRLG) 1Vinay

Kumar, 2Divya Dhawan,

1PG

2

Student, ECE Department, PEC University of Technology Chandigarh, India. Assistant Professor, ECE Department, PEC University of Technology Chandigarh, India [email protected], [email protected]

Abstract: In low power circuit design and efficient energy recycling, Reversible logic plays an important role. Reversible logic has become one of the recent emerging research interests contributing to the field of low power dissipating circuit design in the past few years. Few of its application areas include CMOS low power design, optical electronics network security, nanotechnology, quantum computing, and digital signal and image processing. In this paper presented a reversible half adder, half subtractor, full adder, full subtractor, and switch controlled efficient reversible half and full adder/subtractor using the multifunctional reversible logic gate (MRLG). The proposed design is designed and simulated using Cadence Software. Keyword: Cadence Software; Multifunction reversible logic gate (MRLG); Reversible logic, Reversible half adder/subtractor; Reversible full adder/subtractor;

I. INTRODUCTION Moore’s law, that has only outperformed itself in the past, states that, the number of the transistor fabricated in an IC doubles in a period of a year and a half, so does the heat generation arising from the increasing chip density. Hence In the past years the incentives of Reversible logic have become increasingly motivating. During the operation conventional gates dissipate heat on losing a bit. In 1973 C.H Bennett [1], a physicist, demonstrated that when a circuit is designed with reversible logic no energy dissipation takes place. A circuit is reversible if one can recover input data from the output data which means the circuit information is lossless. The general considerations of bijectivity is imposed on the design of reversible logic, which means that the circuit design should have equal number of output and input and one to one mapping. This eliminates the loss of information that is main reason for power dissipation. The unused outputs of reversible gate are called Garbage output similarly Redundant Inputs to reversible gate are called Garbage inputs. Complexity and Performance of reversible circuits/ gate are defined by the following parameters Number of logic gates Number of garbage and constant inputs Number of Garbage outputs. Fan-out is restricted in reversible logic gate. The fanout of each gate is equal to one. If more fan out are required then use a copying gate.

In the end of this paper we get a new reversible logic gate so as to produce minimum no. of garbage output, lower quantum cost and minimum delay. In Section II we have outlined the related work in terms of gate size, functionality, number of inputs and outputs and logic description. In Section III we have described the proposed New Multifunctional Reversible Logic Gate (MRLG) with CMOS logic structures. In Section IV and give the basic idea of the reversible adder and subtractor. In Section V we have design the circuits of proposed reversible adder and subtractor. The proposed design and MRLG gate has been developed to operate in the voltage range of 1.5 V to 5V with length 180nM and width 2µM transistor with gpdk 180 process. Section VI presents the simulation result and Input output waveform. Conclusion is presented in section VII. II. RELATED WORK Various similar implementation of logic gates have been addressed in [1-14], the classification is defined in terms of its size and functionality. The 1x1 reversible gate is NOT. The 2x2 reversible gate is Feynman. The 3x3 reversible gates are Fredkin, Toffoli, Peres, TR gate, new gate, PRT-1 and PRT-2 and the 4x4 gate includes MKG, TSG and DKG. In Table 1 we have described the logic functionality and a brief description of various gates.

5

International Journal of Advances in Computer and Electronics Engineering Volume: 01 Issue: 02, January, 2016, pp. 5–11

TABLE 1: EXISTING REVERSIBLE LOGIC GATES

Existing Reversible Gate

Gate Size

Feynman 1985 [ 5]

2x2

Toffoli 1980 [15 ]

3x3

Fredkin 1982 [6 ]

3x3

Input/output Definition I(A,B)/ O(P=A,Q=A⊕B)

I(A,B,C)/ O(P=A,Q=B,R=AB⊕ C I(A,B,C)/O(P=A,Q=A’ B ⊕AC, R=A’C’⊕ AB)

Peres 1985 [14 ]

3x3

I(A,B,C)/O(P=A,Q= A⊕ B, R=A⊕ BC

New 2002 [ 2]

3x3

I(A,B,C)/O(P=A,Q= AB⊕ C, R=A’C’⊕ B’)

TR 2011 [ 7]

3x3

PRT-I 2011 [ 16]

3x3

PRT-II 2011 [ 16]

3x3

TSG 2005 [ 8]

4X4

MKG 2007 [ 11]

4X4

DKG 2011 [ 18]

4X4

I(A,B,C)/O(P=A,Q= A⊕ B, R=AB’⊕ C) gate I(A,B,C)/O(P=AB⊕ B’ C, Q=A⊕ B⊕ C, R=AB’ BC) I(A,B,C)/O(P=BC⊕ AC’,Q=A’(B⊕C)+AB, R=C) I(A,B,C,D)/ O(P = A, Q = A’ C’⊕ B’, R = (A’C’⊕ B’) ⊕ Â, S=(A’C’⊕B’) D⊕ (AB⊕ C) I(A,B,C,D)/ O(P = A, Q=C, R = (A’D’⊕ B’) ⊕ C, S = (A’D’⊕ B’)C ⊕ (AB⊕D)) I(A,B,C,D)/ O(P = B, Q = A’C + AD’, R=(A⊕B)(C⊕D) ⊕ CD, S = B⊕C⊕ D)

Functionality XOR, Buffer

Controlled Controlled gate and buffer

Controlled Swap gate Controlled NOT, CCNOT, Copying gate The gate acts as buffer, XOR and AND Buffer, NAND

XOR, XNOR, OR ,AND

OR, XNOR

AND

Description When the control input A is high the output is complementary function of A, otherwise it acts as a buffer When two input A and B are high then output of third terminal is negation of its input, for remaining output terminals act as buffer Output of Q and R will be the swapped value of input B and C when the input A is high When input A is high, output Q will be negation of B and when both A and B are high then the third output R will be the negation of its input C When C input is low the output is XOR by inverting A and B else it acts as AND gate When the input B is inverted by using NOT it produces NAND output functions When input A is high it acts as XNOR/OR and when input C is low it acts as XOR/AND

Quantum cost 1

5

5

4

7

6

6

It acts as OR when input A is high and when C is 1 it acts as XNOR

5

When input C and D applied with 0 it acts as AND gate

14

Buffer, XOR, XNOR and

MKG acts as XOR/AND when A and D is 0 and acts as XNOR when A is high and D is low

Buffer, XOR and

It acts as XOR when A input is low

9

11

6

International Journal of Advances in Computer and Electronics Engineering Volume: 01 Issue: 02, January, 2016, pp. 5–11

III. PROPOSED MULTIFUNCTIONAL REVERSIBLE LOGIC GATE (MRLG) The basic proposed of this Multifunctional Reversible Logic Gate is a reversible logic gate. MRLG have a low power and small delay in design. Fig.1 was the basic approach of this proposed 4X4 reversible MRLG gate. Table 2 shows the MRLG gate truth table. In the truth table of the MRLG input pattern corresponding to a specific output pattern is determined uniquely and to maintain the one-to-one correspondence mapping between the input vector and the output vector. The MRLG input vector is I v = (A, B, C, D) and there output vector is Ov = (P = A, Q = AB ⊕ A’C, R = B⊕ AC, S = B⊕ AC ⊕D). Its CMOS realization is shown in fig. 1.

Fig. 2. CMOS realization of MRLG gate Fig. 1. Proposed MRLG reversible gate.

IV. REVERSIBLE ADDER SUBTRACTOR

TABLE 2: PROPOSED MRLG GATE TRUTH TABLE

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Inputs B C 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

P 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Outputs Q R 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0

S 0 1 0 1 1 0 1 0 0 1 1 0 1 0 0 1

Digital system can perform various arithmetic operations over the binary data. The addition of two binary numbers is performed in a similar as the addition of decimal numbers is performed. Only four cases can occur in adding two binary bits. They are 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, 1 + 1 = 10, that is sum = 0, carry = 1 which we get added to the next higher bit addition. The logic circuit for the addition of two 1-bit numbers is called as half adder, and the logic circuit that adds three 1- bit numbers is called as full adder. The subtractor of two binary numbers is performed in similar manner as the subtraction of decimal numbers. Only four cases can occur in subtraction of two binary bits in any position, those are: 0 – 0 = 0, 0 – 1 = 1(with borrow 1), 1 – 0 = 1 and 1 – 1 = 0. The logic circuit for the subtraction of two 1bit numbers is called as half subtractor, the logic circuit which performs the subtraction of two 1- bit numbers, taking into account the borrow of the pervious stage , is called as full subtractor. Reversible Half Adder The Reversible logic circuit for the addition of two 1-bit numbers is called as Reversible half adder it has two 1-bit inputs and two outputs, viz. sum and carry as shown in fig.3 The basic working of reversible half adder is perform on AND & XOR operation.

6

International Journal of Advances in Computer and Electronics Engineering Volume: 01 Issue: 02, January, 2016, pp. 5–11

Fig3 Block diagram of half adder

The truth table of half- adder is given in table 3, where A and B are the inputs, and Sum and carry are the outputs. Thus the outputs is : Sum = A ⊕ B and Carry = A’ B TABLE 3 TRUTH TABLE OF HALF ADDER

Inputs A 0 0 1 1

B 0 1 0 1

SUM 0 1 1 0

Outputs CARRY 0 0 0 1

Reversible Half Subtractor The half subtractor performs the subtraction of two 1-bit numbers. Its subtracts B (subtrahead) from A (minuend). It has two 1-bit inputs and two outputs as difference and borrow as shown in fig.4.

Fig.4 Block diagram of half subtractor

The truth table of half subtractor is given in Table 4 , where A,B are the inputs and difference and borrow are the outputs. Thus the output is Difference = A⊕ B Borrow A’ B TABLE 4: TRUTH TABLE OF HALF SUBTRACTOR

Inputs A 0 0 1 1

B 0 1 0 1

Outputs Difference Borrow 0 0 1 0 1 0 0 1

Reversible Full adder A reversible half adder has two 1-bit inputs and there is no provision to add a carry which could have been generated from lower bit order addition. This limitation of half adder is overcome in full adder. The reversible full adder has provision to add a carry.

Fig.5 Block diagram of full adder

Let us consider A and B are two inputs C is the carry generated from the previous order bit addition; S (sum) and Cout (carry) are the output of the reversible full adder. The truth table of full adder is given in Table 5 . Thus the output is Sum = A ⊕ B ⊕C Carry = AB + BC + CA TABLE 5: TRUTH TABLE OF FULL ADDER

A 0 0 0 0 1 1 1 1

Inputs B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Sum 0 1 1 0 1 0 0 1

Outputs Carry 0 0 0 1 0 1 1 1

Full subtractor A half subtractor has only two 1-bit inputs and there is no provision for subtraction of borrows which may be generated from lower order bit subtraction. This limitation of half sebtractor is overcome in full subtractor.the full subtractor has provision to take into account a borrow. Let us consider A is 1-bit minuend, B is 1-bit subtrahend, Cin is borrow from the previous stage, Difference and borrow are output of full- subtractor. Fig.6 shows the block diagram of full subtractor. The truth table of reversible full subtractor is given in table 6 .Tthus the output is Difference = A B C Borrow = A’ B + BC + A’C

Fig.6 Block diagram of full subtractor

7

International Journal of Advances in Computer and Electronics Engineering Volume: 01 Issue: 02, January, 2016, pp. 5–11

TABLE 6 TRUTH TABLE OF REVERSIBLE FULL SUBTRACTOR

A 0 0 0 0 1 1 1 1

Input B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Output Difference Borrow 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 1

7D) Reversible full adder

V. PROPOSED DESIGN In Fig.7 shows the design of half adder, subtractor, half adder/subtractor, full adder, subtractor, and full adder/subtractor using MFRG Gate.

7E) Reversible full subtractor 7A) MFRG gate as half adder

7B) MFRG gate as half subtractor

7F) Reversible full adder / subtractor Fig.7 Design of half adder, subtractor, half adder/subtractor, full adder, subtractor, and full adder/subtractor using MFRG Gate.

VI. RESULTS AND DISCUSSION

7C) Reversible half adder / subtractor

The proposed design is simulated using Cadence software. Input and Output waveform of half adder, half subtractor, half adder/subtractor, full adder, full subtractor, and full adder/subtractor shown in fig.8. In Table 7 Shows the average power dissipation calculated for the entire input bit pattern. In comparison of different techniques, the advantage of this design is not only depends on transistor count, delay, and power but also on delay product) and PDP (power and delay product) values. The comparisons of transistors count, Power dissipation, Delay, and PDP are shown in Table 7.

8

International Journal of Advances in Computer and Electronics Engineering Volume: 01 Issue: 02, January, 2016, pp. 5–11

8D) Reversible full adder 8A) Reversible half adder

8E)

reversible full subtractor

8B) Reversible half subtractor

8F) Reversible full adder / subtractor Fig. 8 Input and output waveform half adder, subtractor, half adder/subtractor, full adder, subtractor, and full adder/subtractor 8C) Reversible half adder/ subtractor

9

International Journal of Advances in Computer and Electronics Engineering Volume: 01 Issue: 02, January, 2016, pp. 5–11

TABLE 7. SYNTHESIS RESULTS OF HALF ADDER, SUBTRACTOR, HALF ADDER/SUBTRACTOR, FULL ADDER, SUBTRACTOR, AND FULL ADDER/SUBTRACTOR

MRL G gate count Half Adder

Half Subtra-ctor Half Adder/ Subtractor

Full Adder

Full subtractor Full Adder/ Subtra-ctor

Garbage outpu t

1

2

1

2

3

5

4

2

4

2

5

11

Appli -ed voltage 1.5 2 3 4 1.5 2 3 4 1.5 2 3 4 1.5 2 3 4 1.5 2 3 4 1.5 2 3 4

Avg. power dissipati on (µW) 6.634 19.09 92.88 260.3 6.741 17.87 76.31 209.7 173.5 502.3 1873 4424 111 337.4 1336 3354 53.14 127.3 414.9 986.3 271.7 709.7 2459 5606

Delay (ns) (avg.) 197.6 242.7 381.9 448.9 24.97 17.51 24.92 24.99 37.64 37.51 37.44 37.49 370.0 413.6 469.5 520.6 312.2 369.0 480.6 541.4 240.5 417.5 678.9 536.1

VII. CONCLUSION The reversible addition or subtraction of two binary numbers is performed in a similar as the addition of decimal numbers is performed. The half adder, subtractor, half adder/subtractor, full adder, subtractor, and full adder/subtractor designed using reversible logic with CMOS and pass transistor switch enables the circuit in providing better performance with low power consumption and minimum delay time with supply voltage 1.5 V to 4 V. By using of MFRL gate adder and subtractor with reduced power dissipation. The retival of the input data from the output therefore generated is created highly possible by the use of the garbage values. Hence efficient arithmetic operation, reversible logic gates are effective than the conventional methods. The arithmetic operation in the digital form using the reversible logic gates the loss of information is zero. The simulation is done on cadence software with transistor length 180nM and width 2µM transistor with gpdk 180 process.

1. Bennett, C.H., (1973), “Logical Reversibility of Computation”, IBM Journal Research and Development, 525-532. 2. Azad Khan, M.H, (2002), “Design of Full-Adder with Reversible Gates”, International Conference on Computer and Information Technology, pp. 515-519. 3. Bisdounis, L., D. Gouvetas and O. Koufopavlou, (1998), “A comparative study of CMOS circuit design styles for low-power high-speed VLSI circuits”. International Journal of Electronics, pp.599-613. 4. Chatzigeorgiou, A. and S. Nikolaidis, (2001), “Modeling the operation of pass transistor and CPL gates”, International Journal Electronics, 977-1000 5. Feynman, R., (1985,) “Quantum Mechanical Computers”, Optic News, pp. 11-20. 6. Fredkin, E. and T. Toffoli, (1982), “Conservative Logic”, International Journal of Theoretical Physics, pp.219-253. 7. Himanshu Thapliyal and Nagarajan Ranganathan, (2011), “A New Design of the Reversible Subtractor circuit”, 11th IEEE international Conference Nanotechnology, 8. Himanshu Thapliyal and M.B. Srinvas, (2005), “Novel Reversible TSG gate and Its Application for Designing Components of Primitive Reversible/ Quantum ALU”, ICICS. 9. Krishnaveni, D. and M. Geetha Priya, (2011) “Design of Reversible Serial and Parallel Novel Adder/Subtractor”, International Journal of Engineering Science and Technology; (IJEST). 10. Landauer, R., (1961), “Irreversibility and Heat Generation in the Computing Process”, IBM Journal Research and Development, pp.183-191. 11. Majid haghparast and Keivan Navi, (2007),“A Novel Reversible Full Adder Circuit for Nanotechnology Based Systems”, Journal of Applied Sciences, pp.3995-4000. 12. Maslov, D., D.M. Miller and. G.W. Dueck, (2007) “Techniques for the Synthesis of Reversible Toffoli Networks”, ACM Transaction Design Automated Electronic System. 13. Morgenshtein, A, A. Fish and I.A. Wagner, (2002) “Gate-diffusion input (GDI): A power-efficient method for digital combinatorial circuits”, IEEE Transaction on VLSI, pp.566-581. 14. Peres, A., (1985),“Reversible Logic and Quantum Computers”, Physical Review, pp. 3266-3276.

REFERENCES 10

International Journal of Advances in Computer and Electronics Engineering Volume: 01 Issue: 02, January, 2016, pp. 5–11

15. Tofffoli, T. (1980), “Reversible computing”, Tech Memo MIT/LCS/LM-151, MIT Lab for computer science. 16. Rasmi, S.B. and Tilak B.G., (2011), “Transistor implement of reversible PRT gates”, international Journal of Engineering Science and Technology. 17. V. V. Zhirnov, R. K. Cavin, J. A. (2003), “Hutchby, and G. I. Bourianoff, ―Limits to binary logic switch scaling—A Gedanken model”, Proc.IEEE, vol. 91, no, 11, pp. 1934–1939, 18. T. Ogriro, A. Alhazov, T. Tanizawa, and K. Morita, (2010), “Universality of 2-state 3-symbol reversible logic elements—A direct simulation method of a rotary element”, Workshop Natural Comput. (IWNC2009), Proc. Inform. Commun. Technol. (PICT), vol. 2, pp. 252–250. 19. T. Sasao and K. Nimoshita, (1979), Conservative logic elements and their universality, IEEE Trans. Comput., vol. C-28, no. 9, pp. 682–685. 20. J. E. Rice, (2005) Project in reversible logic, Dept. Math. Comput. Sci., Univ.Lethbridge, Lethbridge, AB, Canada, Tech. Rep. TR-CSJR1. 21. Kumar Vinay, Dhawan Divya, (2015), “An approach To Design of Reversible Synchronous Counters Using Pseudo Reed – Muller Expression”, IRJETERM, vol.1 issue 8, pp. 37-48. 22. Kumar Vinay, Dhawan Divya, (2016), “An Approach to Design a New Multifunctional Reversible Logic Gate (MRLG)”, International Journal of Innovative Research in Computer and Communication Engineering, vol.4 issue 5 pp. 9249- 9256. Authors Biography Vinay Kumar, is a PG Student, Department of ECE in PEC University of Technology Chandigarh, India. He completed his B.Tech in department at IET Dr. RML Avadh University, Faizabad U.P, India. Mrs. Divya Dhawan is currently working as Asst. Professor in ECE Department of PEC University of Technology Chandigarh, India. She has a teaching experience of nearly 18 years. She is a member of IEEE, ISTE, and IEI. Her research interests include Optical Communication, Photonics Systems and Digital system design.

11

Loading...