Design of Low Power CMOS FULL SUBTRACTOR - IJISET

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IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. 1 Issue 6, August 2014. www.ijiset.com ISSN 2348 – 7968

Design of Low Power CMOS FULL SUBTRACTOR K. Prasad Babu#1, S. Ahmed Basha#2, H.Devanna #3 #1

E.C.E. Department, Assistant Professor, #2Assistant Professor, #3Associate Professor JNTU Anantapur. University India St.John’s College of Engineering & Technology, Yemmiganur, 518360, Kurnool, Andhra Pradesh,India .

Abstract Complementary metal–oxide–semiconductor is widely used in manufacturing of IC. CMOS application is felt in microprocessor, microcontrollers, memories, many digital circuits. And are also used for several analog circuits. Due to high noise immunity and low static power consumption CMOS circuits are widely preferred with other logic circuits. CMOS circuits employ p-type and ntype MOSFETs to implement logic gates and other digital circuits. In this Paper we are designing Low power full subtractor using CMOS circuits, with various technologies compared with power dissipation individually. Keywords: CMOS, FULL-SUBTRACTOR, Low-Power, Technologies.

1.

Introduction

The subtraction of two binary numbers may be accomplished by taking the complement of the subtrahend and adding it to the minuend.. The full-subtractor is a combinational circuit which is used to perform subtraction of three bits. It has three inputs, A (minuend) and B(subtrahend) and C (subtrahend) and two outputs D (difference) and B (borrow). The Truth table is as show below A B C DIFFERENCE BORROW 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 The Conventional Full Subtractor using gates is as shown below.

D=A B Borin Borout = Borin (A B)+A.B Section 2. is about implementation part of full subtractor using CMOS gates and its operation with the truth table of various input combinations. Section 3 shows the implementation of Layout. Section 4 is the analog simulation. Section 5 deals the result table of various technologies with power dissipation used by us . Section 6 shows the conclusion and futurescope In this paper we are designing the basic CMOS full subtractor and applying the various technologies. The scaling of Complementary Metal Oxide Semiconductor (CMOS) transistors has so far provided lower cost and higher performance circuits. However, further progress of integration scale will be hindered by a variety of physical effects. The most important effects are the increase in power consumption and the decrease in reliability 0–0. Switching power dissipated by a CMOS device is given by the formula

2. Implementation In this paper we are designing and the full subtractor using CMOS gates. The basic gate functionality is implemented without any degradation in the outputs individually. Initially we start with CMOS implementation of EXOR gate, AND gate, Inverter, OR gate. All these modules are integrated. The CMOS FULLSUBTRACTOR is as shown below

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IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. 1 Issue 6, August 2014. www.ijiset.com ISSN 2348 – 7968

Circuit Operation

Timing Diagram

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IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. 1 Issue 6, August 2014. www.ijiset.com ISSN 2348 – 7968

3. Layout The layout is stick diagrammatic representation of CMOS full subtractor showing NMOS , PMOS, P-diffussion, Metal, Connect, N-diffussion Layers. With A,B,C as the inputs and Difference, Borrow as the outputs.

CMOS 90nm

CMOS 0.12um

4. Analog Simulation It is the pictorial representation of corresponding inputs with the outpus, mentioning the power dissipation. We represent CMOS 0.12um, CMOS 90nm, CMOS 70nm, CMOS 45nm, CMOS 32nm technologies.

CMOS 70nm

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IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. 1 Issue 6, August 2014. www.ijiset.com ISSN 2348 – 7968

CMOS 45nm

5. RESULT Table

Sl.No Technology & No.Of Metal

Vdd volts

1

0.12µm & 6

1.2-2.5

2

90nm & 6

1.00-2.5

3

70nm & 6

0.70-2.5

4 5

45nm & 8

0.4- 1.80 0.351.20

32nm & 8

Power Dissipati on 38.140µ W 27.493 µW 11.903 µW 4.45 µW 3.600 µW

6. Conclusion & Future scope From the above table we conclude that CMOS FULL SUBTRACTOR with 32nm technology is having low power dissipation when compared with other technologies. Further reduction in power dissipation can be achieved with lowest technologies and voltage scaling without degradation of functionality.

CMOS 32nm

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IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. 1 Issue 6, August 2014. www.ijiset.com ISSN 2348 – 7968

References [1] Milind Gautam, Shyam Akashe," Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique”, 2013 International Conference on Computer Communication and Informatics (ICCCI -2013), Jan. 04 – 06, 2013, Coimbatore, INDIA. [2] K.Navi, O. Kavehei, M. Rouholamini, A. Sahafi, S. Mehrabi, N.Dadkhai, "Low-Power and High-Performance I-bit CMOS Full Adder Cell",Journal of Computers, Academy Press, vol. 3, no. 2, Feb. 2008 J. Clerk Maxwell, [3] N.West. K.Eshragian, Principles of CMOS V LSI Design: A systems Perspective, Addison-wesley, 1993.. [4] http://en.wikipedia.org/wiki/Subtractor [5] The International Technology Roadmap for Semiconductors (ITRS), 2004. Available: http://public.itrs.net/ [6] R. Compañó, L. Molenkamp, and D.J. Paul (Eds.), “Technology Roadmap for Nanoelectronics,” European Commission, IST Programme, Future and Emerging Technologies, Microelectronics Advanced Research Initiative MELARI NANO, 2000. Available: http://www.cordis.lu/esprit/src/melna-rm.htm [7] D. J. Frank, “Power constrained CMOS scaling limits,” IBM J. Res. & Dev., vol. 46, 2002, pp. 235–244. [8] V. Beiu, U. Rückert, S. Roy, and J. Nyathi, “On nanoelectronic architectural challenges and solutions,” Proc. IEEE Conf. Nanotech. IEEE-NANO’04, Aug. 2004, pp. 628–631.

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Design of Low Power CMOS FULL SUBTRACTOR - IJISET

IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. 1 Issue 6, August 2014. www.ijiset.com ISSN 2348 – 7968 Design o...

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