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Design and Implementation of Full Subtractor using CMOS 180nm Technology Monikashree T.S1, Usharani .S2, Dr.J.S.Baligar3

1

M.Tech Student, Department of ECE- P.G Studies, Dr. AIT, Bangalore, Karnataka, India. 2 Associate Professor, Department of ECE, Dr .AIT, Bangalore, Karnataka, India. 3 Associate Professor, M .tech Co-ordinator, Department of ECE, Dr .AIT, Bangalore, Karnataka, India.

Abstract — Full subtractor is a combinational digital circuit that performs 1 bit subtraction with borrow-in. The Main objective of this project is to design 1-bit Full Subtractor by using CMOS180nm technology with reduced number of transistors and hence it is efficient in area, speed and power consumption. Two types of simulation or test bench will be performed in order to ensure that the implementation is fully functional. First, a schematic simulation will be performed by means of the “Cadence Schematic Editor and Analog Environment” software. Second, the 1-bit subtractor layout model will be emulated by the “Cadence Virtuoso Editor”. Performing the simulation mainly consists of evaluating the quality of the output signals in terms of voltage levels, to assess the performance of the circuit in terms of speed, area and power usage. Keywords: Cadence, 1-bit Half Subtractor, 1-bit full subtractor, logic gate, Virtuoso. 1.

in fig 2 and its truth table in Table 2.The number of logic gates required to build this subtractor is more which leads to increased number of transistors, hence the area and delay will be large. The need for optimising 1 bit full subtractor using cadence is to reduce the area, delay and power consumption. The CMOS gpdk180nm package incorporates the “Cadence Schematic Editor and Analog Environment” software used to create a schematic diagram and a simulation of our implementation. Moreover, it contains the Cadence Virtuoso Editor which allows us to design the layout of the 1-bit subtractor, as well as to perform the assessment of several performance parameters for the circuit. In addition, transient analysis will be performed. The proposed specifications offer a wide selection varying between two types of implementations, each with an analog kind of difficulty. We chose the design of a 1-bit subtractor in order to minimize the area as much as possible. 2.

SUBTRACTOR

INTRODUCTION

Arithmetic circuits are important part of Digital circuits. In the digital circuits, subtractor is one of the most critical components used in the processor of portable devices [3]. Hence the area and power efficient design of 1-bit Subtractor is necessary for design of small size portable devices. There are various possible logic styles that can give better performance as compared to the basic CMOS logic style. The performance estimation of 1- Bit full Subtractor is based on area, delay and power consumption. The purpose of this work is : 1. To perform the design, full custom implementation and simulation of a 1-bit subtractor at the transistor level by means of CMOS180nm technology [5]. 2. To verify if the circuit can perform with all the possible combinations of the inputs along with the logic function which it is designed for [6]. 3. To evaluate the quality of the output signals in terms of voltage levels. 4. To assess the performance of the circuit in terms of speed, area and power consumption. In the recent years various approaches of CMOS 1- Bit full Subtractor design using various different logic styles have been presented and unified into an integrated design methodology. The Conventional 1 bit full subtractor circuit diagram is shown

A subtractor performs subtraction which is one of the four basic binary operations. In many computers and other kinds of processors, subtractors are used not only for the arithmetic calculations, but are also frequently used in other parts of the processor. The subtractors can be constructed to operate on binary numbers. Depending upon the application of the device or the purpose of the application to be performed, the inputs to the circuit device may vary from two to three. We could possibly use a Half-Subtractor if we have two inputs while for three inputs, a Full-Subtractor can be used. 2.1 1 Bit Half Subtractor A conventional Half-subtractor circuit is a combinational circuit that can be used to subtract one binary digit from another to produce a Difference output and a Borrow output. Functionally, the half subtractor consists of a 2 input XOR Gate, an INVERTER and a 2 input AND gate. The Borrow output here specifies whether a „1‟ has been borrowed to perform the subtraction. The Half-Subtractor at the gate-level and truth table are shown in Fig 1 and Table 1.

1421 ISSN: 2278 – 7798

All Rights Reserved © 2014 IJSETR

International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 5, May 2014

The Truth table and Boolean expression for the two output variables are given below.

. Fig1: Gate Level 1 bit Conventional Half Subtractor.

A

B

Bout

Diff

Comment

0

0

0

0

0-0=0,No borrow

0

1

1

1

0-1=-1,borrow 2, so:2-1=1

1

0

1

0

1-0=1, No borrow

1

1

0

0

1-1=0, No borrow

A

B

Bin

Bout

Diff

Comment

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 0 0 1 1 0 1

0 1 1 0 1 0 0 1

0-0-0=0, No borrow 0-0-1=-1, borrow 2,so:2-1=1 1-0-0=1, No borrow 1-0-1=0, No borrow 0-1-1=-1,(bin=1),borrow2,so:2-1=1 0-1-1=-2,borrow 2,so:2-2=0 1-1-1=0,No borrow 1-1-1=-1,borrow 2,so:2-1=1

Table 2. Truth Table of 1 Bit Full Subtractor.

Table 1. Truth Table of 1 bit half subtractor.

The Boolean expression for the two output variables are given by the equations.

Bout= AB+ ABin+BBin 3.

2.2 One Bit Full Subtractor A 1- Bit full Subtractor is a combinational circuit that performs a subtraction between two binary bits and „1‟ may have been borrowed by a lower significant stage. This circuit has three inputs and two outputs. Let the three inputs be A, B and Bin and Borrow and Difference are two outputs of the 1-bit Subtractor and denoted by Bout and Diff respectively. Circuit diagram of 1-bit full Subtractor is shown in Fig.2.

PROPOSED 1BIT FULL SUBTRACTOR DESIGN

Here the primary goal is to reduce the transistor count in order to reduce area, power and delay parameters. The proposed full subtractor is implemented by cascading two 1 bit half subtractors. In order to build reduced transistor 1 bit subtractor, the idea is to begin with the basic gates. Each individual logic gate used in the circuit is constructed by minimum transistors so as to reduce the circuit area. The performance criteria of each gate is individually investigated and analyzed. The proposed 1 bit subtractor is shown in Fig 3 below.

Fig. 3 Circuit Diagram of proposed 1 bit Full Subtractor.

3.1 Logic Gates Design Fig. 2 Circuit Diagram of conventional 1 bit Full Subtractor.

In subtraction process on two bits, a minuend and a subtrahend are taken into consideration. There may be a „1‟ borrowed from the previous adjacent lower minuend bit. As a result, there are three bits to be handled at the input of a Full-Subtractor, namely the two bits to be subtracted and a borrow bit designated as Bin. There are two outputs, namely the Difference output Diff and the Borrow output Bout. The Borrow output bit tells whether the minuend bit needs to borrow a „1‟ from the next possible higher minuend bit.

The implementation consists of four types of logic gates such as Inverter, 2-input AND gate, 2-input OR gate and 2-input XOR gate. 3.1.1 Inverter An inverter usually output signal representing either “true” or “false”. In this case, the inverter‟s output Vout is true when the input Vin is “false”. Hence Vout is the inverted output of input. The truth table below shows the operation of an inverter. The logic equation for inverter can be written as Vout=Vin.

1422 ISSN: 2278 – 7798

All Rights Reserved © 2014 IJSETR

International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 5, May 2014

Input Vin 0 1

The schematic of all the Logic gates implemented using CMOS 180nm technology is shown in Fig.4 below.

Output Vout 1 0

Table 3: Truth Table of an Inverter.

3.1.2 Two Input AND Gate A 2-input AND gate outputs signal as “true” when inputs A and B are both “true”. Therefore, we can write the 2-input AND logic equation as V= A.B where A, B are inputs and V the output. The truth table below shows the operation of 2-input AND logic gate. Input A

Input B

Output V

0

0

0

0

1

0

1

0

0

1

1

1

Table 4 : Truth table of 2 input AND Gate.

3.1.3 Two Input OR Gate A 2-input OR gate usually outputs signal as “true” when any one inputs A, B or both are “true”, Therefore, we can write the 2-input OR logic equation as V= A + B where A, B are inputs and V is the output. The truth table below shows the operation of 2-input OR logic gate. Input A

Input B

Output V

0

0

0

0

1

1

1

0

1

1

1

1

(a)

(b)

(c)

(d)

Fig 4. Schematics of (a) Inverter (b) 2 Input AND Gate (c) 2 Input OR Gate (d) 2 Input XOR Gate.

3.2

Subtractor Design

In this section we present the transistor level implementation of both 1 bit Half Subtractor and 1 bit Full Subtractor. The pmos and nmos transistors are used to construct the subtractor have their own specifications and are not altered in this work. 3.2.1 One Bit Half subtractor The Schematic of 1 Bit Half subtractor with one XOR gate, an Inverter and an AND gate are implemented at transistor level using Cadence Tool as shown in Fig 5 below.

Table 5 : Truth table of 2 input OR Gate.

3.1.4 Two Input XOR Gate A 2 input XOR gate usually outputs signal as “true” when any one of the inputs A or B is “true”, else false. Therefore, we can write the 2-input XOR logic equation as V= A.B + A.B Where A, B are the inputs and V is the output. The truth table below shows the operation of 2-input XOR logic gate. Input A

Input B

Output V

0

0

0

0

1

1

1

0

1

1

1

0

Table 6: Truth Table of 2 input XOR Gate.

Fig 5: Schematic of transistor level 1 bit Half Subtractor.

3.2.2 One Bit Full Subtractor Here we present both conventional and proposed full subtractor to show the reduced transistor count. Both are implemented in the cadence tool as shown in Fig 6 and Fig 7. 1423

ISSN: 2278 – 7798

All Rights Reserved © 2014 IJSETR

International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 5, May 2014

(c)

(d)

Fig 8: Layouts of (a) Inverter, (b) 2 input AND Gate (c) 2 input OR Gate (d) 2 input XOR Gate.

Fig 6: Schematic of transistor level 1 bit Conventional Full Subtractor.

The implemented layouts of 1-bit half subtractor and 1 bit full subtractor in cadence layout window are shown in Fig 9 and Fig10.

Fig 7: Schematic of transistor level proposed l Bit Full Subtractor. Fig 9: Layout of 1 bit half subtractor.

3. LAYOUTS AND SIMULATION RESULTS 4.1 Layouts The layout of all Basic logic gates are designed using CMOS 180nm technology as shown in Fig 9 below. These layouts help as a reference model to construct a complete full subtractor layout. The implemented layouts of all basic gates used to construct subtractor in cadence layout window are shown in Fig 8.

Fig 10: Layout of proposed 1 bit full subtractor.

4.1

Simulation Results

The implementation of the 1-bit full subtractor circuit will be performed progressively by implementing and creating instances of the components independently. Subsequently, we will merge all the components together to create the 1-bit full subtractor.

(a)

(b)

This section will be divided into two main parts. First, we will perform the step by step implementation and simulation of the 1-bit subtractor by means of the “Cadence Schematic Editor and Analog Environment”. Secondly, we will achieve the same implementation by designing gradually the layout of the 1-bit full subtractor by means of the “Cadence Virtuoso Editor”. Finally, we will record the transient and experimental results for both simulations. 1424

ISSN: 2278 – 7798

All Rights Reserved © 2014 IJSETR

International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 5, May 2014

The simulated results of implemented design of basic gates are shown in Fig 11 below.

Fig 13: Transient responses of proposed 1 bit full subtractor.

(a)

4.

CONCLUSION

Overall, in this experiment different skills and techniques were gained and applied in a fundamental part. Indeed, we will be able to design, implement and successfully analyze the characteristics of a 1-bit full subtractor circuit. The completion of this main task was satisfactory since the theoretical expectations matched our experimental results. The performance of the 1-bit full subtractor was assessed in terms of area, speed and power consumption, also quality of the output signals by comparing the timing measurements of each circuit by means of the propagation delays.

(b)

The total delay and power utilized in proposed 1 bit full subtractor compared to conventional 1 bit subtractor is presented in the table below. Logic Gate

(c)

Number of Transistors

Delay

Power Consumed (micro watt)

Inverter

2

138ps

4.779

2 input AND

6

21.42ps

5.703

2 input OR

6

20.1ps

3.08

2 input XOR

6

20.4ns

6.392

1 bit half subtractor

14

124ps

17.91

1 bit Full Subtractor

34

250ps

47.05

(d) Table 7: Delay and Power summary of proposed 1 bit full subtractor. Fig 11: Transient responses of (a) Inverter, (b) 2 input AND Gate, (c) 2 input OR Gate, (d) 2 input XOR Gate.

The output wave forms of the 1 bit half subtractor and 1 bit full subtractor is shown below.

Fig 12: Transient responses of 1 bit half subtractor.

Logic Gate

Number of Transistors

Delay

Power Consumed (micro watt)

Inverter

2

138ps

4.779

2 input AND

6

21.42ps

5.703

3 input OR

8

89.08ns

1.721

2 input XOR

6

20.4ns

6.392

1 bit Full Subtractor

40

235ps

47.99

Table 8: Delay and Power summary of conventional 1 bit full subtractor.

1425 ISSN: 2278 – 7798

All Rights Reserved © 2014 IJSETR

International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 5, May 2014

REFERENCES [1]

Microelectronic Circuits by Adel S. Sedra and K. C. Smith. Oxford University Press; Fourth Edition.

[2]

Ted Obuchowicsz. A Tutorial on Using the Cadence Schematic Editor and Analog Environment to Create and Simulate a CMOS Converter at the Transistor Level using CMOSIS5 Technology .< http://users.encs.concordia.ca/~ted/>.

[3]

Sung-Mo Kang, Yusuf Leblebici, (2003) CMOS Digital Integrated Circuits: Analysis and Design TATA McGRAW-HILL.

[4]

” Basics of Cmos cell Design” by Elience Sicar & Sonia Delmar Bendhia- Tata McGraw-hill-2005.

[5]

Neil H.E. Weste, Davir Harris,” CMOS VLSI Design: A Circuits and System Perspectives” Addison Wesley – Pearson Education, 3rd Edition, 2004.

[6]

Cadence –Analog and Mixed Signal Labs Manual.

AUTHOR’S PROFILE Monikashree.T.S B.E from MCE, Hassan (Karnataka). M.Tech (pursuing), Department of ECE-PG Studies, Dr. Ambedkar Institute of Technology, Bangalore, Karnataka. Area of interest includes VLSI design and control engineering. Usharani.S Associate Professor, Department of E&C, Dr.Ambedkar Institute of Technology, Bangalore (Karnataka). Currently pursuing P. hd at university of Mysore. Her Area of interest includes signal processing and Image processing. Presently guiding many UG & PG Projects. Dr. J. S. Baligar Associate Professor, Department of E&C-PG Studies, Dr.Ambedkar Institute of Technology, Bangalore (Karnataka).Completed his P. hd from Bangalore University in Electronic Science Department. He has published around 10 papers in international journals. His area of interest includes RF circuit design, micro strip antennas and VLSI design.

1426 ISSN: 2278 – 7798

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