Comparative Study of Half Adder and Subtractor Circuits - IJIRCCE

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ISSN(Online): 2320-9801 ISSN (Print): 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering An ISO 3297: 2007 Certified Organization

Vol.3, Special Issue 5, May 2015

International Conference On Advances in Computer & Communication Engineering (ACCE - 2015)

on 5th & 6th May 2015, Organized by

Comparative Study of Half Adder and Subtractor Circuits based on Quantum-Dot Cellular Automata (QCA) Rani T S, Sourav Karmakar, Ashwini A Metri , Dr.Preeta Sharan Student, Department of ECE, TOCE, Bengaluru, India Student, Department of ECE, St.Peter’s university, Bengaluru, India Asst. Prof, Department of ECE, TOCE, Bengaluru, India Professor, Department of ECE, TOCE, Bengaluru, India ABSTRACT: Quantum- dot cellular automaton (QCA) is an emerging nanotechnology based on the coupling of quantum dots within the cells which are placed at the square corners of a QCA cell. Quantum dot is a Nano-crystal made of semiconductor material that exhibits quantum mechanical properties. The flow of information in the QCA cell is based on the interaction of switching cells. It encodes the binary information as electronic configuration of a cell. In this paper designing of half adder and half subtractor circuits are done based on the proposed XOR gate by QCA implementation. This proposed gate reduces the parameters like area, complexity of circuits by the reduction in number of cells. KEYWORDS: QCA, Nanotechnology, Adders, XOR I

INTRODUCTION

As emerged as a new paradigm Quantum -dot cellular automata beyond CMOS switches to encode binary information [5].To accomplishes the computation in QCA arrays, columbic interaction in the cells is sufficient so wires are not required for the interconnection between cells. Current silicon transistor technology faces challenging problems, such as high power consumption and difficulties in feature size reduction [2]. QCA is one of the alternatives for this as it achieves faster switching speed, high density. QCA logic and circuit designers require a rapid and accurate simulation and design layout tool to determine the functionality of QCA circuits. QCA Designer which provides the functionality of QCA circuits and the designer has the ability to quickly layout a QCA design by providing an extensive set of CAD tools [2] The objective of this paper is to design the half adder and half subtractor circuits using the proposed XOR gate and the newly proposed XOR gate simulation results are compared with the previous designs in terms of number of cells, area, and cell usage and with the simulation time. A. QCA Cell The basic element in the QCA circuits is a QCA cell ,which consists of four quantum-dots positioned at the vertices of a square [3] coupled by the tunneling barriers and it is as shown in Fig. 1(a).These dots are sites in which electrons are able to tunnel between them but cannot leave the cell. Due to the electrostatic force of interaction electrons will tend to occupy diagonally opposite into the quantum dots. The electrons are quantum mechanical particles and they are able to tunnel between the dots in a cell.

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ISSN(Online): 2320-9801 ISSN (Print): 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering An ISO 3297: 2007 Certified Organization

Vol.3, Special Issue 5, May 2015

International Conference On Advances in Computer & Communication Engineering (ACCE - 2015)

on 5th & 6th May 2015, Organized by

Fig. 1(a). QCA cell with four quantum dots with the possible polarizations

By means of electron tunneling exactly two mobile electrons are loaded in the cell and can move to different quantum dots in the QCA tunneling paths in the cell can be represented by the lines connected the quantum-dots in Fig. 1(a). The electrons in the cell that are placed adjacent to each other will interact; as a result, the polarization of one cell will be directly affected by the polarization of its neighboring cells. There are two energetically minimal equivalent arrangement of two electrons in the QCA cell which is denoted by polarizations P=+1, P=-1 represents a binary 1 and 0 respectively .There is an unpolarized state also, in this interdot potential barriers are lowered which reduces the confinement of electrons on the individual quantum dots [5]. The fundamental elements in the QCA logical circuit are majority gate and inverter (MV) [4]. It can be implemented by 5 QCA cells arranged in a cross as shown in Fig. 1(b). By fixing the polarization of one input as logic 1 or 0, we can obtain an OR gate and an AND gate respectively.

Fig. 1(b). QCA Majority gate and its symbol

Fig. 1(c). Inverter types

B. QCA Clocking QCA information flow is a very important thing, here the information flow for the adjacent cells, is in order to control the polarization reactions and effects it is required to hold the polarization of first cell fixed and lower the potential barrier of its adjacent cell in order to let the electrons of adjacent cell relocate .This processing should occur repeatedly throughout the cell to pass the information. QCA Clocking mechanism consists of four clocking zones for the proper functioning of it and is represented as shown in the fig. (2). QCA circuits require clock not only to synchronize & control information flow but also to provide the power to run the circuit since there is no external source for powering cells (serial adders, shifters).With the use of four phases clocking scheme in controlling cells, QCA process and forwards information within cells in an arranged timing scheme.

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ISSN(Online): 2320-9801 ISSN (Print): 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering An ISO 3297: 2007 Certified Organization

Vol.3, Special Issue 5, May 2015

International Conference On Advances in Computer & Communication Engineering (ACCE - 2015)

on 5th & 6th May 2015, Organized by

Fig. 2. Four phases of Clock

II

XOR GATE

XOR gate being the fundamental digital logic component in most of the designing circuits which produces output 1 , when either of its inputs are 1 otherwise 0 .Schematic representation of xor gate in terms of QCA majority gate , and truth table are shown as below .

Fig. 3(a). Schematic XOR gate

Fig.3 (b). Truth table of XOR

XOR gate can be implemented in many ways by using different logics .A representation of XOR Gate by using QCA designer tool and the simulation layout is done as follows for the design in the previous paper [5]

Fig. 4(a). XOR gate

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Fig. 4(b). Simulation result of XOR gate layout

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ISSN(Online): 2320-9801 ISSN (Print): 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering An ISO 3297: 2007 Certified Organization

Vol.3, Special Issue 5, May 2015

International Conference On Advances in Computer & Communication Engineering (ACCE - 2015)

on 5th & 6th May 2015, Organized by A.

Proposed XOR Gate

We have proposed a XOR gate with the objective of reducing area, number of cells and complexity in the existing previous designs .By doing the modification in terms of number of cells and the proper arrangement of it, a new xor gate is proposed and the simulation result is verified by QCA designer tool.

Fig. 5(a). Proposed XOR gate

Fig. 5(b). Simulation result of Proposed XOR gate layout

III

HALF ADDER

Half Adder is implemented by using the combination of XOR gate and And gate .It also can be represented in many ways. Here the half adder circuits are implemented by using different logics in the previous papers .we shall consider those half adder circuits and see the implementations using QCA designer.

Fig. 6(a). Circuit diagram of Half Adder

Fig. 6(b). Truth table of half adder

From the truth table we can obtain the logical expression for SUM and CARRY as follows Sum =AB'+A'B Carry=AB

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ISSN(Online): 2320-9801 ISSN (Print): 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering An ISO 3297: 2007 Certified Organization

Vol.3, Special Issue 5, May 2015

International Conference On Advances in Computer & Communication Engineering (ACCE - 2015)

on 5th & 6th May 2015, Organized by

Fig. 7(a). Half adder

Fig. 7(b). Simulation result of half adder layout

By using the proposed XOR gate it is possible implement the half adder circuit which gives the improvement in number of cell reduction, area and complexity. The simulation results are verified by qca designer. The QCA representation of half adder with the proposed XOR gate and the simulation results are done as follows.

Fig. 8(a). Half adder using proposed XOR gate

Fig. 8(b). Simulation result of half adder proposed XOR layouts

A. Half subtractor Similar to Half adder, half subtractor is also implemented in the same way. The circuit diagram of half subtractor and the truth table is as follows.

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ISSN(Online): 2320-9801 ISSN (Print): 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering An ISO 3297: 2007 Certified Organization

Vol.3, Special Issue 5, May 2015

International Conference On Advances in Computer & Communication Engineering (ACCE - 2015)

on 5th & 6th May 2015, Organized by

Fig. 9(a). Half Subtractor circuit

Fig. 9(b). Truth table of half subtractor

In half subtractor one of the input is inverted remaining structure of the circuit is same as like half adder. As like half adder circuit, half subtractor can also be designed with the proposed xor gate with QCA implementation and the simulation results are obtained and verified.

Fig. 10(a). Half subtractor with proposed XOR gate

Fig.10 (b). Simulation result of half subtractor with proposed XOR layouts

IV COMPARISON OF PROPOSED XOR GATE, HALF ADDER AND HALF SUBTRACTOR CIRCUITS WITH THE PREVIOUS DESIGNS Table 1: Comparison of Existing and Previous Designs [3]

Area (µm2)

No of cells

Xor gate

Proposed

Previous

Proposed

Previous

Proposed

Previous

28

44 (4.a) [5]

0.03

0.07

1

1

34 [10]

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Latency(secs)

0.06

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1

66

ISSN(Online): 2320-9801 ISSN (Print): 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering An ISO 3297: 2007 Certified Organization

Vol.3, Special Issue 5, May 2015

International Conference On Advances in Computer & Communication Engineering (ACCE - 2015)

on 5th & 6th May 2015, Organized by

35[1]

0.04

0.4

Half adder

40

62[3]

0.06

0.08

1

2

Half subtractor

44

62[3]

0.09

0.08

1

2

V

CONCLUSION

By the minimization of number of cells XOR gate is proposed , using this proposed XOR gate half adder and half subtractor circuits are designed and the simulation results are verified with the QCA designer tool .The proposed design reduces cell usage , area and complexity when it is compared with the previous designs. REFERENCES [1] Performance Evaluation of Efficient XOR Structures in Quantum-Dot Cellular Automata (QCA) . Mohammad Rafiq Beigh*, Mohammad Mustafa, Firdous Ahmad: srinagar ,India http://dx.doi.org/10.4236/cs.2013.42020, 2013. [2] Efficient Design of Logical Structures and Functions using Nanotechnology Based Quantum Dot Cellular Automata Design . G.Athisha, S.Karthigai lakshmi. 5, s.l. : International Journal of Computer Applications, 2010, Vol. 3. . [3] A new F-shaped XOR gate and its implementations as novel adder circuits based Quantum-dot cellular Automata (QCA) . Peer Zahoor Ahmad, Firdous Ahmad*, Hilal Ahmad Khan. 3, (J&K) India : IOSR Journal of Computer Engineering (IOSR-JCE) , 2014, Vol. 16. 2278-0661. [4] Novel Code Converters Based On Quantum-dot Cellular Automata (QCA) . Firdous Ahmad, GM Bhat. (J&K) India : International Journal of Science and Research (IJSR) , 2012. 2319-7064 . [5] Design and implementation of quantum cellular automata based novel parity generatorand checker circuits with minimum complexity and cell count. M Mustafa, M R Beigh. Kashmir,India : International Journal of Pure & Applied physics, 2013, Vol. 51. [6] Non Linear Feedback shift registerdesign in quantum- dot cellular automata. M Mustafa, M R Beigh. Kashmir,India : international journal of Pure & Applied Physics, 2014, Vol. 52. [7] Implementation of Code Converters in QCAD . Muthukrishnan, Pallavi A: Moorthy. 06, Andhra Pradesh, India : IJSRD - International Journal for Scientific Research & Development, 2014, Vol. 02. 2321-0613 . [8] Circuit Nanotechnology: QCA Adder Gate Layout Designs . Wani Shah Jahan, Peer Zahoor Ahma2, Peer M A, Khan K A. 02, J & K ,India : IOSR Journal of Computer Engineering (IOSR-JCE) , 2014, Vol. 16. 2278-0661. [9] Design and Optimization of Parity Generator and Parity Checker Based On Quantum-dot Cellular Automata . Santanu Santra, Utpal Ro. 03, s.l. : International Journal of Computer, Control, Quantum and Information Engineering , 2014, Vol. 08. [10] Fijany, N. Toomarian, K. Modarress, and M. Spotnitz, “Bit-serial adder based on quantum dots,” NASA technical report, Jan. 2003. [11] C.S. Lent, P.D. Tougaw, “A device architecture for computing with quantum dots”, Proceedings of the IEEE 85 (4), 541–557, 1997.

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Comparative Study of Half Adder and Subtractor Circuits - IJIRCCE

ISSN(Online): 2320-9801 ISSN (Print): 2320-9798 International Journal of Innovative Research in Computer and Communication Engineering An ISO 3297: 2...

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