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Area efficient Full Subtractor design using CMOS Technology 1

Monikashree T.S, 2Divya A, 3Kesthara V, 4Nithya Shree S

1

Assistant Professor, Department of ITE, Dr.AIT Bangalore, Karnataka, India Assistant Professor, Department of ECE, Dr.AIT Bangalore, Karnataka, India Email: [email protected]

2,3,4

Abstract — Full Subtractor is a combinational digital circuit that performs 1 bit subtraction with borrow-in. The Main objective of this project is to design a 1-bit Full Subtractor by using CMOS180nm technology with reduced number of transistors, and hence it efficiency in area, speed and power consumption. Two types of simulation or test bench will be performed in order to ensure that the implementation is fully functional. First, a schematic simulation will be performed by means of the “Cadence Schematic Editor and Analog Environment” software. Second, the 1-bit subtractor layout model will be emulated by the “Cadence Virtuoso Editor”. Performing the simulation will mainly consist in evaluating the quality of the output signals in terms of voltage levels, to assess the performance of the circuit in terms of speed, area and power usage.

will be large. The need in optimising 1 bit full subtractor using cadence is that, the CMOS gpdk180nm package incorporates the “Cadence Schematic Editor and Analog Environment” software used to create a schematic diagram and a simulation of our implementation. Moreover, it contains the Cadence Virtuoso Editor which will allows us to design the layout of the 1-bit subtractor, as well as to perform the assessment of several performance parameters for the circuit. In addition, transient analysis will be performed. The proposed specifications offered a wide selection varying between two types of implementations, each with an analogous kind of difficulty. We chose the design of a 1-bit subtractor in order to minimize while trying to maintain the area as much as possible.

Keywords: Cadence, 1-bit Half Subtractor, 1-bit full subtractor, logic gate, Virtuoso,

II. SUBTRACTOR

I. INTRODUCTION Arithmetic circuits are important part of Digital circuits. In the digital, circuits subtractor is one of the most critical components used in the processor of portable devices [3]. Hence the area and power efficient design of 1-bit Subtractor is necessary for design of small size portable devices. There are various possible logic styles that can give better performance as compared to the basic CMOS logic style. The performance estimation of 1- Bit full Subtractor is based on area, delay and power consumption. The purpose of this work is [5],[6]. 1. To perform the design, full custom implementation and simulation of a 1-bit subtractor at the transistor level by means of CMOS180nm technology. Subtractor at the transistor level by means of CMOS 180nm technology. 2. To verify if the circuit can perform with all the possible combinations of the inputs alongside the logic function which it is designed for. 3. To evaluate the quality of the output signals in terms of voltage levels. 4. To assess the performance of the circuit in terms of speed, area

A subtractor performs subtraction which is one of the four basic binary operations. In many computers and other kinds of device processors, subtractors are used not only for the arithmetic calculations, but are also frequently used in other parts of the processor. The subtractors can be constructed to operate on binary numbers and represents many binary numbers. Depending upon the application of the device or upon the purpose of the application to be performed, the inputs to the circuit device may vary from two to three. We could possibly use a Half-Subtractor if we have two inputs while for three inputs, a Full-Subtractor can be used. 2.1 1 Bit Half Subtractor A conventional Half-subtractor circuit is a combinational circuit that can be used to subtract one binary digit from another to produce a Difference output and a Borrow output. Functionally, the half subtractor consists of single 2 inputs XOR Gate, INVERTOR Gate and single 2 inputs AND gate. The Borrow output here specifies whether a „1‟ has been borrowed to perform the subtraction. The Half-Subtractor at the gate-level and truth table are shown in Fig 1 and table 1.

In the recent, various approaches of CMOS 1- Bit full Subtractor design by using various different logic styles has presented and unified into an integrated design methodology. The Conventional 1 bit full subtractor diagram is shown in fig1 and its truth table in Table 1.The number of logic gates required are more, it leads in increasing number of transistors, hence the area, delay ________________________________________________________________________________________________ ISSN (PRINT) : 2320 – 8945, Volume -2, Issue -4, 2014 25

ITSI Transactions on Electrical and Electronics Engineering (ITSI-TEEE) ________________________________________________________________________________________________ The Truth table and Boolean expression for the two output variables are given by the equations:

. Fig1: Gate Level 1 bit Conventional Half Subtractor The Truth table and Boolean expression for the two output variables are given by the equations: A

B

Bout

Diff

Comment

0

0

0

0

0-0=0,No borrow

0

1

1

1

0-1=-1,borrow 2, so:2-1=1

1

0

1

0

1-0=1, No borrow

1

1

0

0

1-1=0, No borrow

Table 1: Truth Table of 1 bit half subtractor

2.2 1 Bit Full Subtractor A 1- Bit full Subtractor is a combinational circuit that performs a subtraction between two binary bits and 1 may have been borrowed by a lower significant stage. This circuit has three inputs and two outputs. Let the three inputs are A, B and Bin and Borrow and Difference are two outputs of the 1-bit Subtractor and denoted by Bout and Diff respectively. Logic diagram of 1-bit full Subtractor has been shown in fig.2.

Table 2: Truth Table of 1 Bit Full Subtractor

Bout= AB+ ABin+BBin

III. PROPOSED 1 BIT FULL SUBTRACTOR DESIGN Here the primary goal is to reduce the area and the transistor count in order to reduce area, power, delay parameters. The proposed full subtractor implemented by cascading two 1-bit half subtractor. In order to build reduced transistor 1-bit subtractor, the idea has to begin with the basic gates. Each individual logic gates used in the circuit is constructed by minimum no transistors so as to reduce the circuit area, the performance criteria‟s of each gates are individually investigated, analyzed and their interaction to develop main design. 3.1 Logic Gates Design The implementation consists of four types of logic components such as such as inverters, 2-input AND gates, 2-input OR gates and 2-input XOR gate. 3.1.1

Invertor

An inverter gate usually output signals either representing a “true” or “false”. In this case, the inverter‟s output OUT is true when the input IN is “false”. OUT=IN, where IN is the inverted input and OUT the output. Moreover, the truth table below shows the function of the inverter logic gate:

Fig. 2 Logic Diagram of conventional 1 bit Full Subtractor In subtraction process on two bits, a minuend and a subtrahend, and also takes into consideration whether a „1‟ has been borrowed by the previous adjacent lower minuend bit or not. As a result, there are three bits to be handled at the input of a Full-Subtractor, namely the two bits to be subtracted and a borrow bit designated as Bin. There are two outputs, namely the Difference output D and the Borrow output Bout. The Borrow output bit tells whether the minuend bit needs to borrow a „1‟ from the next possible higher minuend bit.

Input IN 0 1

Output OUT 1 0

Table 3: Truth Table of an Inverter 3.1.2

2 Inputs AND Gate

A 2-input AND gate usually output signals as “true” when inputs A and B are both “true”. Therefore, we can write the 2-input AND logic equation which is simply provided by the following equation below: Vout= A X B where A and B the inputs and vout the output. Moreover, the truth table below shows the operation of the 2-input AND logic gate:

________________________________________________________________________________________________ ISSN (PRINT) : 2320 – 8945, Volume -2, Issue -4, 2014 26

ITSI Transactions on Electrical and Electronics Engineering (ITSI-TEEE) ________________________________________________________________________________________________ Input A 0 0 1 1

Input B 0 1 0 1

Output vout 0 0 0 1

Table 4: Truth Table of 2 inputs AND Gate 3.1.3

2 Inputs OR Gate

A 2-input OR gate usually output signals as “true” when any one inputs A, B or both are “true”, Therefore, we can write the 2-input AND logic equation which is simply provided by the following equation below:

In this section we presented the transistor level implementation of both 1 bit Half Subtractor and 1 bit Full Subtractor. The pmos and nmos transistors used to construct the subtractor are has their own specification, and those are not altered. 3.2.1

1 Bit Half subtractor

The Schematic of 1 Bit Half subtractor with one XOR, Inverter, AND are implemented at transistor level using Cadence Tool is shown in below fig.

Vout= A + B where A and B the inputs and vout the output. Moreover, the truth table below shows the operation of the 2-input OR logic gate: Input A 0 0 1 1

3.1.4

Input B 0 1 0 1

Output vout 0 1 1 1

Fig 4: Schematic of transistor level 1 bit Half Subtractor

Table 5: Truth Table of 2 inputs OR Gate

3.2.2

2 Inputs XOR Gate

Here we presented both conventional and proposed full subtractor to show the reduced transistor count. Both are implemented in same cadence tool.

A 2-input XOR gate usually output signals as “true” when any one inputs A or B are “true”, else false. Therefore, we can write the 2-input AND logic equation which is simply provided by the following equation below:

1 Bit Full Subtractor

Vout= A x B + A x B where A and B are the inputs and Vout is the output. Moreover, the truth table below shows the operation of the 2-input XOR logic gate: Input A 0 0 1 1

Input B 0 1 0 1

Output vout 0 1 1 0

Fig 5: Schematic of transistor level 1 bit Conventional Full Subtractor

Table 6: Truth Table of 2 inputs XOR Gate The schematic of all the Logic gates implemented using CMOS 180nm technology as shown in fig. below:

(a)

(b)

(c)

(d)

Fig 3: Schematics of- (a) Inverter, (b) 2 Inputs AND Gate, (c) 2 Inputs OR Gate, (d) 2 Inputs XOR Gate

Fig 6: Schematic of transistor level proposed l Bit Full Subtractor

3.2 Subtractor Design ________________________________________________________________________________________________ ISSN (PRINT) : 2320 – 8945, Volume -2, Issue -4, 2014 27

ITSI Transactions on Electrical and Electronics Engineering (ITSI-TEEE) ________________________________________________________________________________________________

IV. LAYOUTS AND SIMULATION RESULTS 4.1 Layouts The layout of all Basic logic gates are designed using CMOS 180nm technology as shown in fig below. These layouts help as a reference model to construct a whole full subtractor layout. The implemented layouts of all basic gates used to construct subtractor in cadence layout window are:

Fig 9: Layout of proposed 1 bit full subtractor 4.1

Simulation Results

The implementation of the 1-bit subtractor circuit will be performed progressively by implementing and creating instances of the components independently. Subsequently, we will merge all the components together to create the 1-bit subtractor. At last, we will obtain the 4-bit subtractor by cascading four instances of the 1-bit subtractor created.

(a)

(b)

This section will be broken into two main parts. First, we will perform the step by step implementation and simulation of the 1-bit subtractor by means of the “Cadence Schematic Editor and Analog Environment”. Secondly, we will achieve the same implementation by designing gradually the layout of the 4-bit subtractor by means of the “Cadence Virtuoso Editor”. Finally, we will record the transient and experimental results for both simulations. The simulated results are:

(c)

(d)

(a)

Fig 7: Layouts of (a) Inverter, (b) 2 inputs AND Gate, (c) 2 inputs OR Gates, (d) 2 inputs XOR Gate The implemented layouts of 1-bit half subtractor and 1 bit full subtractor in cadence layout window are: (b)

(c)

(d) Fig 8: Layout of 1 bit half subtractor

Fig 10:Transient responses of (a) Inverter, (b) 2 inputs AND Gate, (c) 2 inputs OR Gates, (d) 2 inputs XOR Gate The resulted output wave forms of the 1 bit half

________________________________________________________________________________________________ ISSN (PRINT) : 2320 – 8945, Volume -2, Issue -4, 2014 28

ITSI Transactions on Electrical and Electronics Engineering (ITSI-TEEE) ________________________________________________________________________________________________ subtractor and 1 bit full subtractor is shown below:

Fig 11: Transient responses of 1 bit half subtractor

Inverter

2

138ps

4.779

2 input AND

6

21.42ps

5.703

2 input OR

6

20.1ps

3.08

2 input XOR

6

20.4ns

6.392

1 bit half subtractor

14

124ps

17.91

1 bit Full Subtractor 1 bit Full Subtractor (convention al)

34

250ps

47.05

40

235ps

47.99

Table 7: Summary of Delay and Power

REFERENCES [1]

Microelectronic Circuits by Adel S. Sedra and K. C. Smith. Oxford University Press; Fourth Edition.

V. CONCLUSION

[2]

Overall, in this experiment different skills and techniques were gained and applied in a fundamental part. Indeed, one can able to design, implement and successfully analyze the characteristics of a 1-bit subtractor circuit. The completion of this main task was entirely satisfactory since the theoretical expectations matched our experimental results. The performance of the 4-bit subtractor was assessed in terms of area, speed, also evaluated the quality of the output signals by comparing the timing measurements of each circuit by means of the propagation delays.

Ted Obuchowicsz. A Tutorial on Using the Cadence Schematic Editor and Analog Environment to Create and Simulate a CMOS Converter at the Transistor Level using CMOSIS5 Technology .< http://users.encs.concordia.ca/~ted/>.

[3]

Sung-Mo Kang, Yusuf Leblebici, (2003) CMOS Digital Integrated Circuits: Analysis and Design TATA McGRAW-HILL .

[4]

” Basics of Cmos cell Design” by Elience Sicar & Sonia Delmar Bendhia- Tata McGraw-hill-2005.

[5]

Neil H.E. Weste, Davir Harris,” CMOS VLSI Design: A Circuits and System Perspectives” Addison Wesley – Pearson Education, 3rd Edition, 2004.

[6]

Cadence –Analog and Mixed Signal Labs Manual.

Fig 12: Transient responses of proposed 1 bit full subtractor

The total delay and power utilized in this project is presented in the below table: Logic Gate

Number of Transistors

Delay

Power Consumed (micro watt)

________________________________________________________________________________________________ ISSN (PRINT) : 2320 – 8945, Volume -2, Issue -4, 2014 29

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